1. Field of the Invention
The present invention relates to a memory control technology for controlling memories in storage devices of computer systems such as DRAMs through which data are written and read in a consecutive access mode, clock-synchronous DRAMs, etc.
2. Description of the Related Art
For example, a DRAM (dynamic RAM) can be operated in a consecutive access mode. In the consecutive access mode, the DRAM receives as activation signals a RAS signal (row address signal), a WE signal (write enable signal), address signals, etc. when data are written. Then, the value of the address signals is incremented by one synchronously with a CAS signal (column address signal), and the synchronously entered data are written to a cell specified by the address signals in the DRAM. Likewise, the DRAM increments by one the value of the address signals synchronously with the CAS signal when data are read. The data are read from a cell specified by the address signals in the DRAM, and are output synchronously with the CAS signal. On the other hand, the clock-synchronous DRAM controls data access by receiving a clock while the above described DRAM controls data access synchronously with the CAS signal. However, these DRAMs have the same fundamental capabilities.
As described above, the present invention relates to a technology of controlling a memory in the consecutive access mode.
Described below are the first technological field practically related to the present invention, and the related arts associated with the present invention.
Assume that a storage system comprises three storage layers, that is, a buffer storage device (cache memory) having a small storage capacity and operating at a high speed in a central processing unit (CPU); an intermediate buffer storage device (secondary cache memory) having an medium-size storage capacity and operating at a moderate speed in a storage control device; and a main storage device having a large storage capacity and operating at a relatively low speed.
Among these storage devices, a block is referred to as a data unit for use in managing and controlling data when they are transferred. The size of a block depends on the combination of storage units from/to which data are transferred. That is, when data are transferred between the buffer storage device and the intermediate buffer storage device, the block size is 64 bytes. When data are transferred between the intermediate buffer storage device and the main storage device, the block size is 512 bytes. The difference in block size comes from the difference in the utilization of each storage device, and the restriction of the memory capacity required for each storage device to control blocks.
Data are transferred between the storage devices in the above described storage system. That is, if desired data are not found in the buffer storage device while the data are transferred between a CPU and the buffer storage device, then a 64-byte block containing the data are read from the intermediate buffer storage device to the buffer storage device. This process is referred to as a move-in. If there is no area for the move-in process because all storage areas are occupied in the buffer storage device, then a block indicating the lowest utilization or the oldest moved-in is written to the intermediate buffer storage device, and an object block is moved in from the intermediate buffer storage device to the storage area previously occupied by the written block. The above described writing operation is referred to as a move-out. Furthermore, if no object data are found in the intermediate buffer storage device in the move-in operation from the intermediate buffer storage device to the buffer storage device, then a 512-byte block containing the data are moved in from the main storage device to the intermediate buffer storage device. If there is no area for the move-in process because all storage areas are occupied in the intermediate buffer storage device, then a block indicating the lowest utilization or the oldest moved-in is moved out to the main storage device, and an object block is moved in from the main storage device to the storage area previously occupied by the written block.
As described above, the present invention relates to a technology of efficiently accessing the main storage device using the DRAM in the consecutive access mode in a storage system in which data are transferred in different block sizes between the buffer storage device and the intermediate buffer storage device, and between the intermediate buffer storage device and the main storage device.
Described below is the first prior art associated with the present invention in the above described first technological field,
FIG. 1 shows the first prior art.
FIG. 1 illustrates the configuration of the main storage device, and the main storage device can be accessed in 8-byte units (word unit). Then, the main storage device comprises two pairs of independently accessed RAMs 101, each comprising bank 0 and bank 1. A pair of the RAMs 101 comprises four DRAM chip sets CS 0.about.CS 3. One DRAM chip set has 1-megaword storage capacity as shown in FIG. 1. Accordingly, the main storage device shown in FIG. 1 has the following storage capacity.
8 bytes.times.1 megaword.times.4 chip sets.times.2 banks=64 megabytes
Assuming that the block size of the data transferred between the above described main storage device and the intermediate buffer storage device (not shown in FIG. 1) is K (for example, 512), all K-byte data in one block are assigned to a set of the RAMs 101 conventionally.
If the intermediate buffer storage device requests a move-out to the main storage device, a storage control device not shown in FIG. 1 realizes a move-out of a block comprising K-byte data by issuing to a set of the RAMs 101 forming the main storage device a write instruction of an L (for example, 64)-byte-data block (K is a multiple of L) for K/L (for example, 8) times while performing a priority process.
If a single CPU uses the main storage device, then the storage control device can issue continuously K/L (for example, 8) times an instruction to write an L-byte data block. Therefore, a set of the RAMs 101 comprising the DRAM which receives the issues process the write instruction in the consecutive access mode.
If a write instruction to write an L-byte-data (L=64) block is issued to a set of the RAMs 101 for practical example, then the RAMs 101 increment the address value by 1 synchronously with a write pulse (a CAS signal or a clock signal), and synchronously write 8-byte data input 8 times continuously via data bus of an 8-byte data width to a cell in the RAMs 101 specified by the address signals. The RAMs 101 can also perform a write process continuously in response to a write instruction to write an L=64 byte data block to be issued after the above described instruction to write an L=64 byte data block. Thus, performing the write instruction to write an L=64 byte data block 8 times realizes a move-out of the block comprising 8 bytes.times.8 times.times.8 times=512 Kbytes.
The above explanation indicates the control made when a move-out to the main storage device is requested by the intermediate buffer storage device. However, the similar control is made when the intermediate buffer storage device requests a move-in from the main storage device.
As described above, all data in a K-byte block are assigned to a set of the RAMs 101 according to the first prior art so that the effect of the consecutive access mode of the RAMs 101 comprising a DRAM can work the most efficiently. In the RAMs 101, a write instruction or a read instruction respectively to write or read an L-byte-data block is executed K/L times continuously in the consecutive access mode.
If a K-byte-data block is transferred between the intermediate buffer storage device and the main storage device, then the storage control device does not issue to the main storage device one write instruction or a read instruction respectively to write or read a K-byte-data block, but issues K/L times the write instruction or the read instruction respectively to write or read an L-byte-data block on the following ground.
If, for example, the buffer storage device in the CPU issues a request to move in an L (for example, 64)-byte-data block in the intermediate buffer storage device, then the storage control device must move in from the main storage device to the intermediate buffer storage device a K (for example, 512)-byte-data block comprising the L-byte data blocks when an object block are not stored in the intermediate buffer storage device. At this time, among the data forming the K-byte data block to be moved in from the main storage device to the intermediate buffer storage device, data of a specific L-byte block must be immediately moved in to the buffer storage device in the CPU from the intermediate buffer storage device. So, the storage control device does not issue one read instruction to read an K-byte-data block, but issues K/L times a read instruction to read L-byte-data block. Thus, moving in by priority from the main storage device to the intermediate buffer storage device at the first read instruction the L-byte data required to be immediately moved in to the buffer storage device in the CPU from the intermediate buffer storage device greatly improves the response of the storage system.
If all storage areas are occupied in the intermediate buffer storage device and there is no area to move data in, and even if a specific K-byte-data block in the intermediate buffer storage device is to be moved out to the main storage device, the storage area in the intermediate buffer storage device should be released by the highest priority for the L-byte-data block to be immediately moved in from the intermediate buffer storage device to the buffer storage device in the CPU. Although the K-byte-data block is moved out from the intermediate buffer storage device to the main storage device, the storage control device significantly issues a write instruction to write data in L-byte data block units to the main storage device.
However, the above described first prior art has the following problems.
According to the first prior art shown in FIG. 1, the consecutive access mode works the most efficiently in the RAMs 101 comprising DRAMs by assigning all data in a K-byte-data block to a set of the RAMs 101 if a single CPU occupies the main storage device.
If the main storage device is shared among a plurality of CPUs, the buffer storage device in each CPU may issue to the intermediate buffer storage device a request for L (for example, 64)-byte-data blocks belonging to a K (for example, 512)-byte-data block separately stored in the main storage device. At this time, data to be immediately moved in by the buffer storage device in each CPU from the intermediate buffer storage device among data forming K-byte-data blocks to be moved in from the main storage device to the intermediate buffer storage device comprise specific L-byte-data blocks. Therefore, it is desirable that the storage control device processes by priority the specific blocks comprising L-byte data requested by each CPU.
As described above, when a K-byte-data block is transferred between the intermediate buffer storage device and the main storage device, the storage control device issues K/L times to the main storage device a write instruction or a read instruction to write or read the L-byte-data block. If a new K-byte-data block must be moved in from the main storage device to the intermediate buffer storage device in association with a request for a specific L-byte-data block from another CPU during the issue of a write instruction or a read instruction to write or read an L-byte-data block to the main storage device K/L times, then the storage control device suspends the K/L-time issue of the write or read instruction and executes the leading read instruction by priority among the K/L read instructions issued to move in the new block. The leading read instruction is to read the L-byte-data block requested by the other CPU.
As described above, even if the K-byte-data block is moved out from the intermediate buffer storage device to the main storage device, the storage control device executes the leading write instruction by priority among K/L write instructions so that a storage area in the intermediate buffer storage device can be obtained by highest priority for the specified L-byte-data block.
However, since all data in the K-byte-data block are assigned to a set of the RAMs 101 (shown in FIG. 1) according to the first prior art, it is necessary in a set of the RAMs 101 to control, that is, activate or stop, access to L-byte-data blocks at separate addresses when two or more blocks, each comprising K-byte data and being simultaneously accessed, are contained in the set of the RAMs 101. When accessed blocks have separate addresses in the RAMs 101 comprising DRAMs, an accessing operation can be activated only after a predetermined pause if the accessing operation is once interrupted. The pause occupies 30.about.40% of the cycle time of the DRAM. According to the first prior art, if there are a plurality of CPUs simultaneously using the main storage device comprising a DRAM, then the cycle time is prolonged when the DRAM is accessed, thereby lowering the throughput of the system.
Described below are the second technological field according to the present invention and the two related prior arts.
Well-known prior arts related to the second technological field are Tokukosho 63-155340, Tokukaihei 1-152547, and Tokukaihei 4-153845, each relating to a memory control technology in a single clock mode used when an entire computer system is tested.
A DRAM requires a periodical refreshing operation to maintain stored data, and uses a timing signal generated by a clock signal which is always in an active state.
While a computer system is being tested, the operation state of the entire system is recognized in a single clock mode by providing each system operation clock for the entire system in a manual operation and observing at each clock an output value of each flipflop, latch, etc. in the system.
To realize an operation in the single clock mode, two types of clock sources are normally provided in the computer system. One is a free run clock (FCLK) which is normally generated in a normal operation state of a computer and is incessantly generated. The other is a gated clock (GCLK), and is generated by having an FCLK pass through a gate controlled according to a clock enable signal. The clock enable signal becomes active predetermined times at a predetermined timing to output the FCLK predetermined times at a predetermined timing. The signal is always active in a normal clock mode other than a single clock mode. Therefore, the phases of the FCLK and GCLK match in the normal clock mode.
To observe the output of a latch, etc. during the test, input clocks should be inactive. Accordingly, if the operation state of the system is recognized, it is desirable that the system comprises latches, etc. operated based on the GCLK. However, if the timing signal and a data signal provided for the DRAM are generated through latches, then a timing cannot be generated for use in a refreshing operation of the DRAM, thereby losing stored data. Therefore, timing signals and data signals provided for the DRAM should be generated through a latch operating according to the FCLK.
As described above, the present invention relates to a technology of providing data from a latch operated according to the GCLK for the DRAM operated according to the FCLK in the consecutive access mode so that the system can be operated as if it were in a normal clock mode even if it actually is in a single clock mode.
Described below is the second prior art practically associated with the present invention in the above mentioned second technological field. The second prior art relates to a technology of controlling a write of data to the main storage device in a DRAM.
FIG. 2 shows the configuration of the second prior art. FIGS. 3A-3D are timing charts showing an operation in the single clock mode of the second prior art. Write data used when a write access is made to a main storage device 202 are transferred from a storage control device 201 to a main storage device 202 through a write data bus 203 provided between the storage control device 201 and the main storage device 202. Each time the GCLK is entered, write data of the amount depending on the bus width of a write data bus are transferred to the main storage device 202.
In the main storage device 202, the write data transferred synchronously with the GCLK are stored in a data register (WD.sub.-- REG) 204 operated according to the GCLK. The output of the register is written to RAMs 205 synchronously with a write timing signal (for example, RAS signals, CAS signals, etc.) operated according to the FCLK.
Assuming that the size of a block of write data simultaneously transferred to the main storage device 202 is L=64 bytes and that the width of the write data bus 203 is 8 bytes, 1-block write data are transferred via the write data bus 203 synchronously with the GCLK after being divided into 8 sections synchronously with the GCLK. Therefore, there are eight sets of WD.sub.-- REGs 204 #0.about.#7 and eight sets of RAMs 205 (banks 0.about.7) provided in the main storage device 202 as shown in FIG. 2.
With the above described configuration, if the write data comprising the first 8 bytes in an L (=64)-byte-block are transferred from the storage control device 201 to the main storage device 202 together with a write instruction STR-8 and an address ADD synchronously with the GCLK, then write data are stored in a flipflop (F/F) 206 and the write instruction STR-8 and the address ADD are stored in an F/F 207 at a timing (referred to as stage 0) synchronous with the GCLK initially generated after the transfer is started in the main storage device 202. At stage 0, a first decoder #1DEC 208 decodes a 3-bit bank address part BANK ADD in the address ADD stored in the F/F 207. As a result, a write data set signal WD.sub.-- SETi (i can be 0.about.7) for the bank address part BANK ADD becomes active. Accordingly, the write data stored in the F/F 206 at stage 0 are stored in the #1 WD.sub.-- REG 204 for the write data set signal WD.sub.-- SETi at a timing (referred to as stage 1) preceded by stage 0 synchronously with the GCLK. The write data are output to the RAMs 205 in the bank i for the #i WD.sub.-- REG 204.
At stage 1, the address ADD stored in the F/F 207 at stage 0 is stored in an F/F 209, and the 3-bit bank address part BANK ADD in the address ADD is decoded by a second decoder (#2DEC) 210. As a result, a selection signal SELi (i can be 0.about.7) for the bank address part BANK ADD becomes active at stage 1 as shown in FIG. 3A.
Furthermore, the selection signal SELi is input to a #i differentiation circuit 211. In the #i differentiation circuit 211, a signal SELiDL shown in FIG. 3B is generated delaying the selection signal SELi by one clock of the FCLK. A write start signal FCLGOi shown in FIG. 3C is generated using the signal SELiDL and the selection signal SELi. The write start signal FCLGOi is stored in a #i F/F 212 synchronously with the FCLK, which is synchronous with the GCLK, immediately after stage 1. An output of the #i F/F 212 is provided for the RAMs 205 in bank i as a #i negative logic RAS signal shown in FIG. 3D. The #i negative logic RAS signal is represented as "RASi" with a horizontal line above in FIGS. 2 and 3A-3D. The character i indicates any number of 0.about.7. The #i negative logic RAS signal is input to a bank i timing generator through a #i F/F 213 operating synchronously with the FCLK. The bank i timing generator generates synchronously with the FCLK a timing signal required by the RAMs 205 in bank i in a single writing operation. As a result, the bank i write data stored in the #i WD REG 204 synchronously with the GCLK at stage 1 are written to the RAMs 205 in bank i synchronously with the FCLK to be generated later.
After the first write data are input to the main storage device 202 synchronously with a GCLK as described above, the second write data are input to the main storage device 202 synchronously with the next GCLK. The write data are written to the RAMs 205 in the bank at the bank address part BANK ADD in the address ADD input together to the main storage device 202. Thus, when write data synchronous with the GCLK are transferred 8 times from the storage control device 201, the RAMs 205 in each bank is sequentially activated and write data are written to each of the RAMs 205.
FIG. 2 shows the configuration for simple explanation in which a write instruction STR-8 and an address ADD are transferred from the storage control device 201 to the main storage device 202 corresponding to each piece of write data. Normally, the write instruction STR-8 and the address ADD are transferred from the storage control device 201 to the main storage device 202 and stored there only when the first 8-byte write data in an L (=64)-byte block are transferred. Each time the second piece and subsequent write data are transferred from the storage control device 201 to the main storage device 202, the value of the bank address part BANK ADD in the address ADD is incremented by 1 in the main storage device 202, and a write address is generated for each piece of the write data.
If the main storage device 202 of the above described configuration is operated in a normal clock mode, then the phases of the FCLK and GCLK match. If, by contrast, the main storage device 202 is operated in a single clock mode, then the input intervals T'0 (not always at regular intervals) of the GCLK are much longer than the cycle T of the FCLK as shown in FIGS. 3A-3D. Thus, in such a single clock mode, the input timing of the write data to the main storage device 202 and the specification timing of a write address to the RAMs 205 are synchronous with the GCLK in the main storage device 202 according to the second prior art shown in FIG. 2 because the #1DEC 208 for outputting the write data set signal WD.sub.-- SETi for use in controlling the WD.sub.-- REG 204 and the #2DEC 210 for outputting the selection signal SELi for use in generating a write address operate synchronously with the GCLK. Thus, similar operations are realized in a normal clock mode and a single clock mode in the main storage device 202 according to the second prior art.
However, the above described second prior art has the following problems.
According to the second prior art shown in FIG. 2, the WD.sub.-- REG 204 which is specified by the bank address part BANK ADD and can be operated independently and the corresponding RAMs 205 are provided for each piece of write data transferred synchronously with the GCLK of 1 clock. They are sequentially activated synchronously with the GCLK. Thus, according to the second prior art, writing an L (=64)-byte block requires the 8-bank RAMs 205. If a write process in a single bank requires time longer than 8 cycles of the FCLK, then the L (=64)-byte block transferred from the storage control device 201 to the main storage device 202 within the time of 8 cycles of the GCLK having the same phase as the FCLK in the normal clock mode cannot be written consecutively. In this case, each of the RAMs 205 requires more banks. Thus, the second prior art has the problem of a large-scale hardware.
Described below is the third prior art related to the present invention in the second technological field. The third prior art relates to the technology of controlling data read from the main storage device comprising DRAMs.
FIG. 4 shows the configuration of the main storage device in the third prior art. FIGS. 5A-5C are timing charts showing the operation according to the third prior art.
If the main storage device shown in FIG. 4 is operated in the normal clock mode, then a read instruction FCH 64 input from the storage control device (not shown in FIG. 4) to the main storage device is stored in an F/F 305 operated synchronously with the GCLK, and then input to #0.about.#7 memory control signal generation circuits 307 operated synchronously with the FCLK through a selection circuit (SEL) 306. An F/F 309 is described later. As a result, memory control signals such as negative logic RAS signals, etc. are provided for any of RAMs 301 from any of the #0.about.#7 memory control signal generation circuits 307 synchronously with the FCLK.
The #0.about.#7 RAMs 301 comprise DRAMs. The RAMs 301 activated by the memory control signal generation circuits 307 output 8-byte read data RD consecutively 8 times synchronously with the FCLK in the consecutive access mode after the cycle time of the RAMs 301 has passed. The read data RD are output to a single read signal line connected to #0.about.#7 read data registers MDR 302 based on the DOT logic, etc.
When a read data selection signal RDSEL is output from a 3-bit counter (not shown in FIG. 4) which operates synchronously with the FCLK and is decoded by a decoder (DEC) 308, read data set signals RDST 0.about.7 output from the DEC 308 become active sequentially.
As a result, 8 pieces of read data RD output from any of the RAMs 301 are sequentially stored in the #0 .about.#7 MDRs 302.
When selection data are output from a 3-bit counter (not shown in FIG. 4) which operates synchronously with the GCLK and are decoded by a decoder (not shown in FIG. 4), selection signals DMPX.sub.-- RD 0.about.7 to be sequentially active are provided by the decoder for a selection circuit (SEL) 303. As a result, an output of each of the 8 MDRs 302 is selected by the SEL 303 and output to the storage control device (not shown in FIG. 4) as 8 pieces of 8-byte read data MRD through an F/F 304 and a read data bus (not shown in FIG. 4) which operate synchronously with the GCLK and have the data width of 8 bytes.
Thus, according to the configuration shown in FIG. 4, a single read instruction FCH 64 outputs 64 -bytes (8 bytes.times.8 pieces) read data from the main storage device via a read data bus of 8-byte data width. Accordingly, the single read instruction FCH allows the read data bus to be occupied for the time 8.tau., where .tau. indicates the cycle of the GCLK and is equal to the cycle of the FCLK in the normal clock mode. When the read instruction FCH 64 is provided for the main storage device, the storage control device (not shown in FIG. 4) is suspended for 8.tau. from the issue of the first request REQ 0 of the read instruction FCH 64 to the issue of the second request REQ 1 of the read instruction FCH 64 as shown in FIGS. 5A-5C.
In FIG. 4, 8 RAMs 301 are provided for a set of 8 MDRs 302. This configuration does not directly relate to the present invention described later. It is so designed because the cycle of the DRAMs forming the RAMs 301 is almost double the access time of the storage control device to the main storage device, and therefore a main storage device normally comprises a plurality of RAMs to secure the throughput. If the cycle of a single RAM group 301 is longer than 8.tau., then a plurality of RAM groups 301 are provided and the read instruction FCH 64 is issued for each of the RAM groups 301 at every 8.tau., thereby obtaining memory read data MRD in series. If, by contrast, the cycle of a single RAM group 301 is shorter than 8.tau., then the read instruction FCH 64 is issued to the same RAM group 301 at each 8.tau., thereby obtaining memory read data MRD in series. Thus, the present invention described later relates to a memory control method in which activation intervals of the RAMs are determined according to the amount of data read from the main storage device by a single read instruction FCH and the data transfer width of a read data bus regardless of the parameters indicating the access time of the RAMs 301, the cycle of the RAMs 301, etc.
FIGS. 5A-5C show an example of an operation timing of the main storage device shown in FIG. 4 in a normal clock mode. In FIGS. 5A-5C, the clock timing of the GCLK equals that of the FCLK (in the normal clock mode) at 0.tau..about.21.tau.
First, a request REQ0 of the read instruction FCH 64 is issued to the RAMs 301 in bank 0 at 0.tau. as shown in FIG. 5A. Then, memory control signals such as negative logic RAS signals are provided for the RAMs 301 in bank 0 at 1.tau. as shown FIG. 5B. As a result, 8 pieces of read data RD corresponding to the request REQ 0 of the read instruction FCH 64 are read from the RAMs 301 of bank 0 and are sequentially stored in the #0.about.#7 MDR 302 at 9.tau..about.16.tau.. Then, as shown in FIG. 5A, the 8 pieces of the memory read data MRD are sequentially output to the read data bus at 10.tau..about.17.tau.. Thus, the time 17.tau. is required to output all 8-byte data specified by the read instruction FCH 64 as memory read data MRD since the read instruction FCH 64 has been entered. The required time is referred to as a read cycle.
While the above described operation is being performed, the second request REQ 1 is issued to the RAMs 301 in bank 1 at 8.tau., that is, 8.tau. after the first request REQ 0 has been issued at 0.tau. for the read instruction FCH 64 as shown in FIG. 5A. Then, the memory control signals such as the #1 negative logic RAS signal, etc. are provided for the RAMs 301 in bank 1 at 9.tau. as shown in FIG. 5B. As a result, at 17.tau..about.24.tau., 8 pieces of read data RD specified by the request REQ 1 of the read instruction FCH 64 are read from the RAMs 301 in bank 1 and sequentially stored in the #0.about.#7 MDRs 302. Then, as shown by in FIG. 5C, 8 pieces of memory read data MRD are sequentially output via a read data bus at 18.tau..about.25.tau. after 10.tau..about.17.tau. when memory read data MRD specified by the request REQ 0 of the read instruction FCH 64 are output.
However, the above described third prior art has the following problem.
As mentioned above, after the F/F 305 in the main storage device shown in FIG. 4 has received the first request of the read instruction FCH 64 from the storage control device (not shown in FIGS. 5A-5C) at the 0-th GCLK, the RAMs 301 are activated through the memory control signal generation circuit 307 operating synchronously with the FCLK. As a result, 8 pieces of read data RD output from the RAMs 301 in series are stored in the #0.about.#7 MDRs 302. In the single clock mode, the cycle of the GCLK is much longer than the cycle of the FCLK as shown in FIG. 6A-6C. Accordingly, a negative logic RAS signal is generated according to the FCLK and input to the RAMs 301 based on the GCLK entered when the first request of the read instruction FCH 64 is issued as shown in FIGS. 6A-6D, and 8-byte read data RD output from the RAMs 301 are set in the MDR 302 synchronously with the FCLK. These operations are completed long before the next GCLK is entered. The first contents of the 8 pieces of the data stored in the MDR 302 are read when the 10th GCLK is entered based on the first entry of the request of the read instruction FCH 64 as shown in FIG. 6D. The last contents of the 8 pieces of the data stored in the MDR 302 are read when the 17th GCLK is entered based on the entry of the first request of the read instruction FCH 64 as described above.
When the 8th GCLK is entered based on the entry of the first request of the read instruction FCH 64, the next request of the read instruction FCH 64 is entered. As in the entry of the first request of the read instruction FCH 64, the RAMs 301 are activated synchronously with the FCLK and the contents of the 8 pieces of data in the MDR 302 are replaced with the data specified by the second read instruction FCH 64 before the 8 pieces of data in the MDR 302 specified by the first read instruction FCH 64 are output. Therefore, the data output from the MDR 302 after the 10th GCLK is input based on the entry of the first request of the read instruction FCH 64 are not the data specified by the first read instruction FCH 64, but those specified by the second read instruction FCH 64.
Since the third request of the read instruction FCH 64 is entered when the 16th GCLK is entered based on the entry of the first request of the read instruction FCH 64, the data output from the MDR 302 when the 17th GCLK is entered based on the entry of the first request of the read instruction FCH 64 are not the data specified by the first read instruction FCH 64, but those specified by the third read instruction FCH 64.
Thus, if the main storage device is operated in the single clock mode according to the third prior art without any modification, then the memory read data MRD specified by each request of the read instruction FCH 64 cannot be output correctly.
To avoid the problem, a subsequent instruction cannot be entered after a read instruction is issued in the single clock mode until all of plural pieces of read data output in series from the RAMs in the main storage device have been completely stored in the buffer (F/F) which is operated synchronously with the GCLK and located first at the output side of the main storage device. The stop time equals the above described read cycle, that is, 7.tau. (GCLK) in the case of the configuration shown in FIG. 4. With this configuration, as described above, a single read instruction FCH 64 outputs read data comprising 8 bytes.times.8 pieces=64 bytes via a read data bus of an 8-byte data width, and a single read instruction FCH 64 occupies the read data bus for 8.tau.. Therefore, the storage control device outputs the read instruction FCH 64 at intervals of 8.tau.. Thus, the maximum number of the read instructions input to the main storage device within the read cycle is 3.
Based on the consideration above, the shift registers 309 are provided conventionally as shown in FIG. 4 to delay the entry of the read instruction FCH 64 to the RAMs 301 by the time corresponding to the above mentioned read cycle.
With the configuration, a single clock mode notice signal (SINGM) is input to the SEL 306 from the clock control unit (not shown in FIG. 4) provided in, for example, the storage control device in advance by the time equal to the read cycle before the main storage device enters the single clock mode. After the entry of the signal, the SEL 306 selects the output of the shift registers 309, not the output of the F/F 305. Simultaneously, the shift registers 309 are provided with the GCLK for their operations. Afterwards, the read instruction FCH 64 input to the main storage device is delayed by the time equal to the read cycle by the shift registers 309, and then entered in the memory control signal generation circuit 307. Thus, the memory control signal generation circuit 307 operated synchronously with the FCLK and the RAMs 301 are activated after being delayed by the time equal to the read cycle. Accordingly, memory read data MRD can be output correctly according to each of the read instructions FCH 64.
If the operation of the main storage device is returned from the single clock mode to the normal clock mode, a clock is switched from the GCLK to the FCLK to operate the shift registers 309, and then the read instruction FCH 64 in the shift registers 309 is output to the memory control signal generation circuit 307 through the SEL 306, and the single clock mode notice signal (SINGM) entered in the SEL 306 is nullified. Thus, data can be prevented from being lost when the single clock mode is switched to the normal clock mode.
However, the above described prior art has the serious problem of a complicated circuit configuration because it needs entering a control signal line such as a single clock mode notice signal (SINGM) from a clock control unit provided in, for example, the storage control device to the main storage device.
Furthermore, the state transition of, for example, the main storage device is performed between the single clock mode and the normal clock mode under undesirably complicated timing control according to the above explained prior art, thereby causing a problem of difficult timing change.
Since the operations of the main storage device are different between the normal clock mode and the single clock mode, it is very difficult to analyze in the single clock mode the faults in the main storage device which has occurred in the normal clock mode.